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for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 1 HMCAD1050-80 v01.0411 dual 13/12-bit 65/ 80 msps a /d converter functional diagram features ? 13-bit resolution ? 65/80 m s p s maximum s ampling r ate ? ultra-low power dissipation: 85/102 mw ? 72 db snr @ 8 mhz fi n ? internal r eference circuitry ? 1.8 v core s upply v oltage ? 1.7 - 3.6 v i/ o supply voltage ? parallel cm os output ? 9 x 9 mm 64-pin qf n (lp9 e ) package ? dual channel t ypical a pplications ? handheld communication, pm r , s d r ? medical imaging ? portable t est e quipment ? digital o scilloscopes ? baseband / if communication ? v ideo digitizing ? ccd digitizing general description t he HMCAD1050-80 is a high performance low power dual analog-to-digital converter (adc). t he adc employs internal reference circuitry, a cm os control interface, cm os output data and is based on a proprietary structure. digital error correction is employed to ensure no missing codes in the complete full scale range. s everal idle modes with fast startup times exist. e ach channel can be independently powered down and the entire chip can either be put in s tandby mode or power down mode. t he different modes are optimized to allow the user to select the mode resulting in the lowest possible energy consumption during idle mode and startup. t he HMCAD1050-80 has a highly linear t ha optimized for frequencies up to 70 mhz. t he differential clock interface is optimized for low jitter clock sources and supports l v d s , l v p e cl, sine wave and cm os clock inputs. pin compatible with hmcad1040-40, hmcad1040-80 and hmcad1050-40. figure 1. functional block diagram
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 2 HMCAD1050-80 v01.0411 dual 13/12-bit 65/ 80 msps a /d converter e lectrical specifcations dc e lectrical specifcations a v dd=1.8 v , d v dd=1.8 v , d v ddck=1.8 v , ov dd=2.5 v , 65/80m s p s clock, 50% clock duty cycle, -1dbfs 8mhz input signal, 13 bit output, unless otherwise noted parameter condition min typ max unit dc accuracy n o missing codes guaranteed o ffset error midscale offset 1 l s b gain error full scale range deviation from typical 6 %fs gain matching gain matching between channels. 3 sigma value at worst case conditions 0.5 %fs d n l differential nonlinearity (12-bit level) 0.2 l s b i n l integral nonlinearity (12-bit level) 0.6 l s b v cm common mode voltage output v a v dd /2 v analog input input common mode analog input common mode voltage v cm -0.1 v cm +0.2 v full scale range, n ormal differential input voltage range, 2 v pp full scale range, o ption differential input voltage range, 1 v (see section r eference v olt - ages) 1 v pp input capacitance differential input capacitance 2 pf bandwidth input bandwidth 500 mhz power supply core s upply v oltage s upply voltage to all 1.8 v domain pins. s ee pin confguration and description 1.7 1.8 2 v i/ o s upply v oltage o utput driver supply voltage ( ov dd). s hould be higher than or equal to core s upply v oltage ( v ov dd v d v dd ) 1.7 2.5 3.6 v
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 3 HMCAD1050-80 v01.0411 dual 13/12-bit 65/ 80 msps a /d converter a c e lectrical specifcations - 65 msps a v dd=1.8 v , d v dd= 1.8 v , d v ddck= 1.8 v , ov dd=2.5 v , fs =65 m s p s clock, 50% clock duty cycle, -1 dbfs 8 mhz input signal, 13 bit output, unless otherwise noted. parameter condition min typ max unit performance snr s ignal to n oise r atio f i n = 8 mhz 71.6 72.6 dbf s f i n = 20 mhz 71.8 dbf s f i n =~ fs /2 71.5 dbf s f i n = 40 mhz 70.4 dbf s sn d r s ignal to n oise and distortion r atio f i n = 8 mhz 70.5 71.7 dbf s f i n = 20 mhz 71.7 dbf s f i n =~ fs /2 71.1 dbf s f i n = 40 mhz 70 dbf s s fd r s purious free dynamic r ange f i n = 8 mhz 75 81 dbc f i n = 20 mhz 84 dbc f i n =~ fs /2 79 dbc f i n = 40 mhz 77 dbc hd2 s econd order harmonic distortion f i n = 8 mhz -85 -95 dbc f i n = 20 mhz -95 dbc f i n =~ fs /2 -95 dbc f i n = 40 mhz -95 dbc hd3 t hird order harmonic distortion f i n = 8 mhz -75 -81 dbc f i n = 20 mhz -84 dbc f i n =~ fs /2 -79 dbc f i n = 40 mhz -79 dbc eno b e ffective number of bits f i n = 8 mhz 11.4 11.6 bits f i n = 20 mhz 11.6 bits f i n =~ fs /2 11.5 bits f i n = 40 mhz 11.3 bits crosstalk s ignal crosstalk between channels, f i n 1 = 8mhz, f i n 0 = 9.9mhz -95 db power supply analog supply current 32.8 ma digital supply current digital core supply 5 ma o utput driver supply 2.5 v output driver supply, sine wave input, f i n = 1 mhz, ck_ e x t enabled 8.2 ma o utput driver supply 2.5 v output driver supply, sine wave input, f i n = 1 mhz, ck_ e x t disabled 6.6 ma analog power dissipation 59 mw digital power dissipation ov dd = 2.5 v , ~5pf load on output bits, f i n = 1 mhz, ck_ e x t disabled 25.5 mw t otal power dissipation ov dd = 2.5 v , ~5pf load on output bits, f i n = 1 mhz, ck_ e x t disabled 84.5 mw power down dissipation 9.3 w s leep mode 1 power dissipation, s leep mode one channel 55.3 mw s leep mode 2 power dissipation, s leep mode both channels 20.4 mw clock inputs max. conversion r ate 65 m s p s min. conversion r ate 3 m s p s
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 4 HMCAD1050-80 v01.0411 dual 13/12-bit 65/ 80 msps a /d converter a c e lectrical specifcations - 80 msps a v dd=1.8 v , d v dd=1.8 v , d v ddck=1.8 v , ov dd=2.5 v , fs =80m s p s clock, 50% clock duty cycle, -1dbfs 8mhz input signal, 13 bit output, unless otherwise noted. parameter condition min typ max unit performance snr s ignal to n oise r atio f i n = 8 mhz 70.4 72 dbf s f i n = 20 mhz 71.7 dbf s f i n = 30 mhz 71.2 dbf s f i n =~ fs /2 70.7 dbf s sn d r s ignal to n oise and distortion r atio f i n = 8 mhz 69.5 70.5 dbf s f i n = 20 mhz 70.5 dbf s f i n = 30 mhz 70.4 dbf s f i n =~ fs /2 70.3 dbf s s fd r s purious free dynamic r ange f i n = 8 mhz 74 77 dbc f i n = 20 mhz 78 dbc f i n = 30 mhz 78 dbc f i n =~ fs /2 78 dbc hd2 s econd order harmonic distortion f i n = 8 mhz -80 -95 dbc f i n = 20 mhz -90 dbc f i n = 30 mhz -90 dbc f i n =~ fs /2 -85 dbc hd3 t hird order harmonic distortion f i n = 8 mhz -74 -77 dbc f i n = 20 mhz -78 dbc f i n = 30 mhz -78 dbc f i n =~ fs /2 -78 dbc eno b e ffective number of bits f i n = 8 mhz 11.3 11.4 bits f i n = 20 mhz 11.4 bits f i n = 30 mhz 11.4 bits f i n =~ fs /2 11.4 bits crosstalk s ignal crosstalk between channels, f i n 1 = 8mhz, f i n 0 = 9.9mhz -95 db power supply analog supply current 39.7 ma digital supply current digital core supply 6 ma o utput driver supply 2.5 v output driver supply, sine wave input, f i n = 1 mhz, ck_ e x t enabled 9.4 ma o utput driver supply 2.5 v output driver supply, sine wave input, f i n = 1 mhz, ck_ e x t disabled 7.7 ma analog power dissipation 71.5 mw digital power dissipation ov dd = 2.5 v , 5pf load on output bits, f i n = 1 mhz, ck_ e x t disabled 30 mw t otal power dissipation ov dd = 2.5 v , 5pf load on output bits, f i n = 1 mhz, ck_ e x t disabled 101.5 mw power down dissipation 9.1 w s leep mode 1 power dissipation, s leep mode one channel 66.4 mw s leep mode 2 power dissipation, s leep mode both channels 24.1 mw clock inputs max. conversion r ate 80 m s p s min. conversion r ate 3 m s p s
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 5 HMCAD1050-80 v01.0411 dual 13/12-bit 65/ 80 msps a /d converter digital and t iming specifcations a v dd= 1.8v , d v dd= 1.8v , d v ddck= 1.8v , ovdd= 2.5v , conversion r ate: max specifed, 50% clock duty cycle, -1 dbf s input signal, 5 pf capacitive load on data outputs, unless otherwise noted parameter condition min typ max unit clock inputs duty cycle 20 80 % high compliance cmos , l vds , l vpecl, s ine wave input range differential input swing 0.4 vpp input range differential input swing, sine wave clock input 1.6 vpp input common mode voltage keep voltages within ground and voltage of ov dd 0.3 v ov dd -0.3 v input capacitance differential 2 pf timing t pd s tart up time from power down mode to active mode 900 clock cycles t slp s tart up time from s leep mode to active mode 20 clock cycles t ovr o ut of range recovery time 1 clock cycles t ap aperture delay 0.8 ns ?rms aperture jitter < 0.5 ps t la t pipeline delay 12 clock cycles t d o utput delay (see timing diagram). 5pf load on output bits 3 10 ns t dc o utput delay relative to ck_ext (see timing diagram) 1 6 ns logic inputs v hi high level input v oltage. v ov dd 3.0v 2 v v hi high level input v oltage. v ov dd = 1.7 v C 3.0v 0.8 v ov dd v v li low level input v oltage. v ov dd 3.0v 0 0.8 v v li low level input v oltage. v ov dd = 1.7 v C 3.0v 0 0.2 v ov dd v i hi high level input leakage current 10 a i li low level input leakage current 10 a c i input capacitance 3 pf logic outputs v ho high level output v oltage v ov dd -0.1 v v l o low level output v oltage 0.1 v c l max capacitive load. post-driver supply voltage equal to digital supply voltage v ov dd = v d vdd 5 pf c l max capacitive load. post-driver supply voltage above 2.25 v (1) 10 pf (1) t he outputs will be functional with higher loads. however, it is recommended to keep the load on output data bits as low as possible to keep dynamic currents and resulting switching noise at a minimum
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 6 HMCAD1050-80 v01.0411 dual 13/12-bit 65/ 80 msps a /d converter t iming diagram figure 2: t iming diagram a bsolute maximum r atings absolute maximum ratings are limiting values to be applied for short periods of time. e xposure to absolute maximum rating conditions for an extended period of time may reduce device lifetime. t able 1: pin pin rating a v dd a vss -0.3 v to +2.3 v d v dd d vss -0.3 v to +2.3 v a vss , d vss ck, d vss , ovss d vss -0.3 v to +0.3 v ov dd ovss -0.3 v to +3.9 v ipx, i n x, analog inputs and outputs a vss -0.3 v to +2.3 v digital outputs ovss -0.3 v to +3.9 v ckp, ck n d vss ck -0.3 v to +3.9 v digital inputs ovss -0.3 v to +3.9 v o perating temperature -40 to +85 oc s torage temperature -60 to +150 oc s oldering profle qualifcation j- st d-020 e l e c trost a t ic sens i t i ve d ev ic e o b serve ha n dli n g p re cau t i ons s tresses above those listed under absolute maximum r atings may cause permanent damage to the device. t his is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specifcation is not implied. e xposure to absolute maximum rating conditions for extended periods may affect device reliability.
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 7 HMCAD1050-80 v01.0411 dual 13/12-bit 65/ 80 msps a /d converter pin confguration and description figure 3: package drawing, 64-pin qf n or t qfp t able 2: pin function pin # name description 1, 18, 23 d v dd digital and i/ o -ring pre driver supply voltage, 1.8 v 2 cm_ e x t common mode voltage output 3, 9, 12 a v dd analog supply voltage, 1.8 v 4, 5, 8 a vss analog ground 6, 7 ip0, i n 0 analog input channel 0 (non-inverting, inverting) 10, 11 ip1, i n 1 analog input channel 1 (non-inverting, inverting) 13 d vss ck clock circuitry ground 14 d v ddck clock circuitry supply voltage, 1.8 v 15 ckp clock input, non-inverting (format: l v d s , l v p e cl, cm os / tt l, s ine wave) 16 ck n clock input, inverting. for cm os input on ckp, connect ck n to ground. 17, 64 d vss digital circuitry ground 19 ck_ e x t _ en ck_ e x t signal enabled when low (zero). t ristate when high. 20 df r m t data format selection. 0: o ffset binary, 1: t wos complement
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 8 HMCAD1050-80 v01.0411 dual 13/12-bit 65/ 80 msps a /d converter t able 2: pin function pin # name description 21 pd_ n full chip power down mode when low. all digital outputs reset to zero. after chip power up always apply power down mode before using active mode to reset chip. 22 oe _ n _1 o utput e nable channel 0. t ristate when high 24, 41, 58 ov dd i/ o ring post-driver supply voltage. v oltage range 1.7 to 3.6 v 25, 40, 57 ovss ground for i/ o ring 26 d1_0 o utput data channel 1 (l s b, 13 bit output or 1 v pp full scale range ) 27 d1_1 o utput data channel 1 (l s b, 12 bit output 2 v pp full scale range) 28 d1_2 o utput data channel 1 29 d1_3 o utput data channel 1 30 d1_4 o utput data channel 1 31 d1_5 o utput data channel 1 32 d1_6 o utput data channel 1 33 d1_7 o utput data channel 1 34 d1_8 o utput data channel 1 35 d1_9 o utput data channel 1 36 d1_10 o utput data channel 1 37 d1_11 o utput data channel 1 (m s b for 1 v pp full scale range, see r eference v oltages section) 38 d1_12 o utput data channel 1 (m s b for 2 v pp full scale range) 39 orn g_1 o ut of r ange fag channel 1. high when input signal is out of range 42 ck_ e x t o utput clock signal for data synchronization. cm os levels 43 d0_0 o utput data channel 0 (l s b, 13 bit output or 1 v pp full scale range) 44 d0_1 o utput data channel 0 (l s b, 12 bit output 2 v pp full scale range) 45 d0_2 o utput data channel 0 46 d0_3 o utput data channel 0 47 d0_4 o utput data channel 0 48 d0_5 o utput data channel 0 49 d0_6 o utput data channel 0 50 d0_7 o utput data channel 0 51 d0_8 o utput data channel 0 52 d0_9 o utput data channel 0 53 d0_10 o utput data channel 0 54 d0_11 o utput data channel 0 (m s b for 1 v pp full scale range, see r eference v oltages section) 55 d0_12 o utput data channel 0 (m s b for 2 v pp full scale range) 56 orn g_0 o ut of r ange fag channel 0. high when input signal is out of range 59 oe _ n _0 o utput e nable channel 0. t ristate when high 60, 61 cm_ e x t bc_1, cm_ e x t bc_0 bias control bits for the buffer driving pin cm_ e x t 00: o ff 01: 50ua 10: 500ua 11: 1ma 62, 63 s lp_ n _1, s lp_ n _0 s leep mode 00: s leep mode 01: channel 0 active 10: channel 1 active 11: both channels active
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 9 HMCAD1050-80 v01.0411 dual 13/12-bit 65/ 80 msps a /d converter r ecommended u sage analog input t he analog inputs to the HMCAD1050-80 is a switched capacitor track-and-hold amplifer optimized for differ - ential operation. o peration at common mode voltages at mid supply is recommended even if performance will be good for the ranges specifed. t he cm_ e x t pin provides a voltage suitable as common mode voltage reference. t he internal buffer for the cm_ e x t voltage can be switched off, and driving capabilities can be changed by using the cm_ e x t bc control input. figure 4 shows a simplifed drawing of the input net - work. t he signal source must have sufficiently low output impedance to charge the sampling capacitors within one clock cycle. a small external resistor (e.g. 22 o hm) in series with each input is recommended as it helps reducing transient currents and dampens ringing behavior. a small differential shunt capacitor at the chip side of the resistors may be used to provide dynamic charging currents and may improve perfor - mance. t he resistors form a low pass flter with the capacitor, and values must therefore be determined by requirements for the application. figure 4: input confguration dc-coupling figure 5 shows a recommended confguration for dc- coupling. n ote that the common mode input voltage must be controlled according to specifed values. pref - erably, the cm_ e x t output should be used as refer - ence to set the common mode voltage. figure 5: dc coupled input with buffer t he input amplifer could be inside a companion chip or it could be a dedicated amplifer. s everal suitable single ended to differential driver amplifers exist in the market. t he system designer should make sure the specifcations of the selected amplifer is adequate for the total system, and that driving capabilities comply with the HMCAD1050-80 input specifcations. detailed confguration and usage instructions must be found in the documentation of the selected driver, and the values given in fgure 5 must be varied according to the recommendations for the driver. ac-coupling a signal transformer or series capacitors can be used to make an ac-coupled input network. figure 6 shows a recommended confguration using a transformer. figure 6: t ransformer coupled input make sure that a transformer with sufficient linearity is selected, and that the bandwidth of the transformer is appropriate. t he bandwidth should exceed the sampling rate of the adc with at least a factor of 10. it is also important to minimize phase mismatch between the differential adc inputs for good hd2 per - formance. t his type of transformer coupled input is the preferred confguration for high frequency signals as most differential amplifers do not have adequate performance at high frequencies. magnetic coupling between the transformers and pcb traces may impact channel crosstalk, and must hence be taken into account during pcb layout. if the input signal is travel - ing a long physical distance from the signal source to the transformer (for example a long cable), kick-backs from the adc will also travel along this distance. if these kick-backs are not terminated properly at the source side, they are refected and will add to the input signal at the adc input. t his could reduce the adc performance. t o avoid this effect, the source must effectively terminate the adc kick-backs, or the travel - ing distance should be very short. if this problem could not be avoided, the circuit in fgure 8 can be used. figure 7 shows ac-coupling using capacitors. r esis - tors from the cm_ e x t output, r cm, should be used to bias the differential input signals to the correct volt -
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 10 HMCAD1050-80 v01.0411 dual 13/12-bit 65/ 80 msps a /d converter age. t he series capacitor, ci, form the high-pass pole with these resistors, and the values must therefore be determined based on the requirement to the high-pass cut-off frequency. figure 7: ac coupled input n ote that startup time from s leep mode and power down mode will be affected by this flter as the time required to charge the series capacitors is dependent on the flter cut-off frequency. if the input signal has a long traveling distance, and the kick-backs from the adc not are effectively terminated at the signal source, the input network of fgure 8 can be used. t he confguration in fgure 8 is designed to attenuate the kickback from the adc and to provide an input impedance that looks as resistive as possible for frequencies below n yquist. v alues of the series inductor will however depend on board design and conversion rate. in some instances a shunt capaci - tor in parallel with the termination resistor (e.g. 33pf) may improve adc performance further. t his capacitor attenuate the adc kick-back even more, and minimize the kicks traveling towards the source. however, the impedance match seen into the transformer becomes worse. figure 8: alternative input network clock input and jitter considerations t ypically high-speed adcs use both clock edges to generate internal timing signals. in the hmcad1050- 80 only the rising edge of the clock is used. hence, input clock duty cycles between 20% and 80% are acceptable. t he input clock can be supplied in a variety of formats. t he clock pins are ac-coupled internally. hence a wide common mode voltage range is accepted. differ - ential clock sources as l v d s , l v p e cl or differential sine wave can be connected directly to the input pins. for cm os inputs, the ck n pin should be connected to ground, and the cm os clock signal should be con - nected to ckp. for differential sine wave clock, the input amplitude must be at least 800 m v pp. t he quality of the input clock is extremely important for high-speed, high-resolution adcs. t he contribu - tion to snr from clock jitter with a full scale signal at a given frequency is shown in equation 1, snr jitter = 20 log (2 ? in ? t ) (1) where fi n is the signal frequency, and t is the total rms jitter measured in seconds. t he rms jitter is the total of all jitter sources including the clock generation circuitry, clock distribution and internal adc circuitry. for applications where jitter may limit the obtainable performance, it is of utmost importance to limit the clock jitter. t his can be obtained by using precise and stable clock references (e.g. crystal oscillators with good jitter specifcations) and make sure the clock dis - tribution is well controlled. it might be advantageous to use analog power and ground planes to ensure low noise on the supplies to all circuitry in the clock distribution. it is of utmost importance to avoid cross - talk between the adc output bits and the clock and between the analog input signal and the clock since such crosstalk often results in harmonic distortion. t he jitter performance is improved with reduced rise and fall times of the input clock. hence, optimum jitter performance is obtained with l v d s or l v p e cl clock with fast edges. cm os and sine wave clock inputs will result in slightly degraded jitter performance. if the clock is generated by other circuitry, it should be re-timed with a low jitter master clock as the last operation before it is applied to the adc clock input. digital outputs digital output data are presented on parallel cm os form. t he voltage on the ov dd pin set the levels of the cm os outputs. t he output drivers are dimensioned to drive a wide range of loads for ov dd above 2.25 v , but it is recommended to minimize the load to ensure as low transient switching currents and resulting noise as possible. in applications with a large fanout or large capacitive loads, it is recommended to add external buffers located close to the adc chip. t he timing is described in the t iming diagram section. n ote that the load or equivalent delay on ck_ e x t
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 11 HMCAD1050-80 v01.0411 dual 13/12-bit 65/ 80 msps a /d converter always should be lower than the load on data outputs to ensure sufficient timing margins. t he digital outputs can be set in tristate mode by set - ting the oe _ n signal high. t he HMCAD1050-80 employs digital offset correc - tion. t his means that the output code will be 4096 with shorted inputs. however, small mismatches in para - sitics at the input can cause this to alter slightly. t he offset correction also results in possible loss of codes at the edges of the full scale range. with no offset correction, the adc would clip in one end before the other, in practice resulting in code loss at the oppo - site end. with the output being centered digitally, the output will clip, and the out of range fags will be set, before max code is reached. when out of range fags are set, the code is forced to all ones for overrange and all zeros for underrange. n ote that the out of range fags ( orn g) will behave differently for 12 bit and 13 bit output. for 13 bit output orn g will be set when digital output data are all ones or all zeros. for 12-bit output the orn g fags will be set when all twelve bits are zeros or ones and when the thirteenth bit is equal to the rest of the bits. data format selection t he output data are presented on offset binary form when df r m t is low (connect to ovss ). s etting df r m t high (connect to ov dd) results in 2s comple - ment output format. details are shown in table 3. t he data outputs can be used in three different con - fgurations. ? normal mode: all 13 bits are used. m s b is dx_12 and l s b is dx_0. t his mode gives optimum performance ? 12-bit mode: t he l s b is left unconnected such that only 12 bits are used. m s b is dx_12 and l s b is dx_1. t his mode gives slightly reduced performance due to increased quantization noise. ? reduced full scale range mode: t he full scale range is reduced from 2 v pp to 1 v pp which is equivalent to 6 db gain in the adc frontend. n ote that data are only available in 2s complement format in this mode. m s b is dx_11 and l s b is dx_0. n ote that the codes will wrap around when exceeding the full scale range, and that out of range bits should be used to clamp output data. s ee section r eference v oltages for details. t his mode gives slightly reduced performance reference voltages t he reference voltages are internally generated and buffered based on a bandgap voltage reference. n o external decoupling is necessary, and the reference voltages are not available externally. t his simplifes usage of the adc since two extremely sensitive pins, otherwise needed, are removed from the interface. if a lower full scale range is required the 13-bit output word provides sufficient resolution to perform digital scaling with an equivalent impact on noise compared to adjusting the reference voltages. a simple way to obtain 1.0 v pp input range with a 12-bit output word is shown in table 4. n ote that only 2s complement output data are available in this mode and that out of range conditions must be determined based on a two bit output. t he output code will wrap around when the code goes outside the full scale range. t he out of range bits should be used to clamp the output data for overrange conditions. t able 3: data format description for 2 v pp full scale r ange differential input voltage (ipx - inx) output data: dx_12 : dx_0 (dfrmt = 0, o ffset binary) output data: dx_12 : dx_0 (dfrmt = 1, 2s complement) 1.0 v 1 1111 1111 1111 0 1111 1111 1111 +0.24mv 1 0000 0000 0000 0 0000 0000 0000 -0.24mv 0 1111 1111 1111 1 1111 1111 1111 -1.0 v 0 0000 0000 0000 1 0000 0000 0000
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 12 HMCAD1050-80 v01.0411 dual 13/12-bit 65/ 80 msps a /d converter t able 4: data format description for 1 v pp full scale r ange differential input voltage (ipx - i n x) output data dx_11:dx_0 (df r m t = 0) (2s complement) out of range (use logical and function for &) output data dx_11:dx_0 (df r m t = 1) (2s complement) out of range (use logical and function for &) > 0.5 v 0111 1111 1111 dx_12 = 1 & dx_11 = 1 0111 1111 1111 d_12 = 0 & d_11 = 1 0.5 v 0111 1111 1111 0111 1111 1111 +0.24m v 0000 0000 0000 0000 0000 0000 -0.24m v 1111 1111 1111 1111 1111 1111 -0.5 v 1000 0000 0000 1000 0000 0000 < -0.5 v 1000 0000 0000 dx_12 = 0 & dx_11 = 0 1000 0000 0000 dx_12 = 1 & dx_11 = 0 operational modes t he operational modes are controlled with the pd_ n and s lp_ n pins. if pd_ n is set low, all other control pins are overridden and the chip is set in power down mode. in this mode all circuitry is completely turned off and the internal clock is disabled. hence, only leak - age current contributes to the power down dissipa - tion. t he startup time from this mode is longer than for other idle modes as all references need to settle to their fnal values before normal operation can resume. t he s lp_ n bus can be used to power down each channel independently, or to set the full chip in s leep mode. in t his mode internal clocking is disabled, but some low bandwidth circuitry is kept on to allow for a short startup time. however, s leep mode represents a signifcant reduction in supply current, and it can be used to save power even for short idle periods. startup initialization t he HMCAD1050-80 must be reset prior to normal operation. t his is required every time the power supply voltage has been switched off. a reset is per - formed by applying power down mode. wait until a stable supply voltage has been reached, and pull the pd_ n pin for the duration of at least one clock cycle. t he input clock must be running continuously during this power down period and until active operation is reached. alternatively the pd pin can be kept low during power-up, and then be set high when the power supply voltage is stable. t he input clock should be kept running in all idle modes. however, even lower power dissipation is pos - sible in power down mode if the input clock is stopped. in this case it is important to start the input clock prior to enabling active mode.
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 13 HMCAD1050-80 v01.0411 dual 13/12-bit 65/ 80 msps a /d converter o utline drawing t able 6: 9x9 mm qfn (64 pin lp9) dimensions symbol millimeter inch min typ max min typ max a 0.9 0.035 a1 0 0.01 0.05 0 0.000 0.002 a2 0.65 0.7 0.026 0.028 a3 0.2 re f 0.008 re f b 0.2 0.25 0.3 0.008 0.01 0.012 d 9.00 bsc 0.354 bsc d1 8.75 bsc 0.344 bsc d2 3.79 3.99 4.19 0.149 0.157 0.165 l 0.3 0.4 0.5 0.012 0.016 0.02 e 0.50 bsc 0.020 bsc 1 0 12 0 12 f 1.9 0.075 g 0.24 0.42 0.6 0.010 0.017 0.024
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 14 HMCAD1050-80 v01.0411 dual 13/12-bit 65/ 80 msps a /d converter package i nformation part number package body material lead finish msl [1] package marking [2] HMCAD1050-80 r oh s -compliant low s tress injection molded plastic 100% matte s n level 2a a s d0500 xxxx xxxx [1] m s l, peak t emp: t he moisture sensitivity level rating classifed according to the j e d e c industry standard and to peak solder temperature. [2] proprietary marking xxxx, 4-digit lot number xxxx

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